Standard complementary metal-oxide semiconductor (CMOS) technology uses a polysilicon gate with a silicon oxide gate insulator in which the polysilicon is doped to establish a p-type field effect transistor (PFET) or n-type FET (NFET). Current CMOS technology is transitioning to metal gates that use thin, high dielectric constant (high-K) gate insulators, which increases capacitance.
In partially depleted semiconductor-on-insulator (PDSOI) substrates, body contacts are made using gate extensions or extensions that do not make up part of the active gate region. The gate extension(s) add further capacitance to the FET, which slows performance. The presence of the high-K material and/or silicon germanium (SiGe) under the gate extensions magnifies the capacitance issue.